1. Technical Field
Embodiments of the present invention relate to semiconductor memory devices, and more particularly to an ultra low power consumption random access memory cell that is designed for minimal leakage operation.
2. Discussion of the Related Art
The ongoing demand for ultra low power consumption integrated circuits lead to sub-threshold and near-threshold operation of digital circuits. These approaches utilize very low supply voltages for digital circuit operation, decreasing the dynamic power quadratically, and sufficiently reducing leakage currents. As static power is often the primary factor in a system's power consumption, especially for low to medium performance systems, supply voltage scaling for minimization of leakage currents is essential. Optimal power-delay studies show that the Minimum Energy Point (MEP) is found in the sub-threshold region, where ultra-low power figures are achieved, at the expense of orders-of-magnitude loss in performance.
Low voltage operation of static Complementary Metal Oxide Semiconductor (CMOS) logic is quite straightforward, as its non-ratioed structure generally achieves robust operation under process variations and device mismatch. However, when ratioed designs are put under extreme conditions, maintaining functionality becomes challenging. Global variations change the drive strength ratio between n-channel MOS (nMOS) and p-channel MOS (pMOS) devices, often overcoming the sizing considerations taken into account when designing the circuits. Local mismatch brings an even tougher challenge, as the drive strength ratios between similar devices can be affected, and symmetrically designed circuits can easily lose functionality. At sub and near-threshold supply voltages, these fluctuations in drive strength are often more substantial than the effects of sizing and mobility. Thus a circuit that is fully operational at the typical process corner or when all devices are slow or fast, may not function at the fast nMOS/slow pMOS (aka FS) or fast pMOS/slow nMOS (aka SF) corners. Even if functionality is achieved at all process corners, local mismatch can cause failure.
FIG. 1 shows a circuit diagram of a standard six-transistor static SRAM cell 100 (write and read circuitry not shown here) according to the prior art. SRAM cell 100 is constructed of a pair of cross coupled static CMOS inverters, which are non-ratioed and therefore operational under process variations at very low supply voltages. However, accessing the data stored in the cell is a ratioed process, including a contention between a pull up and a pull down network in both read and write operations. During nominal strong inversion operation, sizing considerations are incorporated to ensure writeability and readability. However, at low voltages, process variations and mismatch cause a loss of functionality. Both theoretical and measured analysis show that standard SRAM blocks are limited to operating voltages of no lower than 700 mV.
FIG. 2 shows a circuit diagram of a standard eight-transistor static SRAM cell 200 according to the prior art. Standard eight-transistor static SRAM cell 200 includes the aforementioned six-transistor circuitry, a two port write configuration that includes two write circuitry (each for writing a logic ‘0’ to either node Q or node QB via nMOS access devices) and a read circuitry with a decoupled read out path. Standard eight-transistor static SRAM cell 200 features read margins equivalent to its hold margins, however its write margins maintain the aforementioned 700 mV supply limitation.